Method for manufacturing semiconductor device

ABSTRACT

To resolve strain in a semiconductor substrate wafer due to high temperature nitriding of a transistor gate insulation film, and to maintain high positional accuracy for a photolithography process. After nitriding processing for a gate insulation film, by performing annealing under a nitrogen atmosphere after formation of a gate electrode film over the entire surface of a semiconductor substrate wafer, strain in the semiconductor substrate wafer is resolved without increasing contamination of the gate insulation film, and high positional precision in a photolithography process after the nitriding process is maintained.

FIELD OF THE INVENTION

[0001] The present invention relates to a manufacturing method for asemiconductor device, and more particularly relates to a method ofmanufacturing a MOS transistor for improving reliability of a gateinsulation film, and a method of manufacturing an EEPROM cell forimproving reliability of a tunnel insulation film.

DESCRIPTION OF THE RELATED ART

[0002] Conventionally, when manufacturing a MOS transistor on asemiconductor substrate, the following process was used in order toimprove reliability of a gate oxidation film.

[0003] First of all, as shown in FIG. 7A, an element separation film 40on a silicon semiconductor substrate 39 and a gate insulation film 41are formed using well known techniques.

[0004] Next, as shown in FIG. 7B, nitriding is carried out for the gateinsulation film using a well known technique. Normally this nitriding iscarried out for a short time at a high temperature, and the reliabilityof the gate insulation film is improved by this process.

[0005] Next, as shown in FIG. 7C, a gate electrode film 42(a) is formedusing a well known technique.

[0006] Continuing on, as shown in FIG. 7D, the gate electrode film 42(a)is patterned and removed by etching to form a gate electrode film 42(b),and a MOS transistor comprising a transistor source/drain 43, aninterlayer insulating film 44, a contact hole 45 and metal wiring 46 isformed by the following well known technique.

[0007] With the manufacturing method of the related art, since thenitriding process is carried out for a short time at a high temperatureafter formation of the gate insulation film, a steep temperaturegradient and the effects of oxygen cause the following problems.

[0008] 1. Strain occurs in a silicon semiconductor substrate wafer, andpositioning precision of a photolithography process is significantlydegraded.

[0009] 2. Slip lines occur in the silicon semiconductor substrate wafer,which are the cause of IC leak defects etc.

[0010] The object of the present invention is to improve a manufacturingmethod to solve the above described problems.

SUMMARY OF THE INVENTION

[0011] In a step of forming a MOS transistor on a semiconductorsubstrate, there is provided, between a process of forming a gateinsulation film and a process of patterning a gate electrode film andremoving the gate electrode film by etching, means for carrying outannealing using inert gas.

[0012] Here, at least one of the following features is also included.

[0013] 1. The inert gas is N₂.

[0014] 2. The temperature of annealing with inert gas is at least 925°C.

[0015] 3. After formation of the insulating gate film, RTA (RapidThermal Annealing) is carried out in a gas atmosphere including at leastone of nitrogen atoms or oxygen atoms.

[0016] 4. The gas atmosphere including at least one of nitrogen atoms oroxygen atoms is N₂O or O₂.

[0017] 5. The temperature of RTA processing is higher than 1000° C.

[0018] 6. After formation of an insulating gate film over the entiresurface of the semiconductor substrate, annealing is carried out usingan inert gas.

[0019] Further, in a step of forming an EEPROM on a semiconductorsubstrate, there is provided, between a process of forming a tunnelinsulation film and a process of patterning a floating gate electrodefilm and removing the floating gate electrode film by etching, means forcarrying out annealing using inert gas.

[0020] Here, at least one of the following features is also included.

[0021] 1. The inert gas is N₂.

[0022] 2. The temperature of annealing with inert gas is at least 925°C.

[0023] 3. After formation of the a tunnel insulating film, RTA (RapidThermal Annealing) is carried out in a gas atmosphere including at leastone of nitrogen atoms or oxygen atoms.

[0024] 4. After formation of a floating electrode film over the entiresurface of the semiconductor substrate, annealing is carried out usingan inert gas.

[0025] With the means described above, the manufacturing method of thepresent invention brings about the following effects.

[0026] 1. Strain of the semiconductor substrate wafer can be resolvedwithout any increase in contamination of the gate insulation film.

[0027] 2. It is possible to maintain high positioning precision in aphotolithography process after nitriding.

[0028] Also, in a step of forming a MOS transistor on a semiconductorsubstrate, there are provided a process of forming a gate insulationfilm and, after forming the gate insulation film, means for carrying outheat treatment in a gas atmosphere including oxygen atoms at atemperature of less than 1000° C.

[0029] Here, at least one of the following features is also included.

[0030] 1. The gas including oxygen atoms is N₂O.

[0031] 2. The gas including oxygen atoms is O₂.

[0032] 3. Between a step of forming the gate insulating film and a stepof carrying out heat treatment in a O₂ atmosphere, heat treatment iscarried out in a NH₃ atmosphere.

[0033] 4. The heat treatment at less than 1000° C. is RTA (Rapid ThermalAnnealing).

[0034] Also, in a step of forming a MOS transistor on a semiconductorsubstrate, there are provided a process of forming a gate insulationfilm and, after forming the gate insulation film, means for carrying outheat treatment in a gas atmosphere including oxygen atoms at atemperature of less than 1000° C.

[0035] Here, at least one of the following features is also included.

[0036] 1. The gas including oxygen atoms is N₂O.

[0037] 2. The gas including oxygen atoms is O₂.

[0038] 3. Between a step of forming the gate insulating film and a stepof carrying out heat treatment in an O₂ atmosphere, heat treatment iscarried out in an NH₃ atmosphere.

[0039]4. The heat treatment at less than 1000° C. is RTA (Rapid ThermalAnnealing).

[0040] With the means described above, the manufacturing method of thepresent invention brings about the following effects.

[0041] 1. There is no strain generated in the semiconductor substratewafer.

[0042] 2. There are no slip lines generated in the semiconductorsubstrate wafer.

[0043] 3. It is possible to maintain high positioning precision in aphotolithography process after nitriding.

BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and other objects as well as advantages of the presentinvention will become clear by the following description of thepreferred embodiments of the present invention with reference to theaccompanying drawings:

[0045]FIGS. 1A to 1E are cross sectional views showing the steps ofmethod of manufacturing a semiconductor device according to a firstembodiment of the present invention;

[0046]FIGS. 2A to 2E are cross sectional views showing the steps ofmethod of manufacturing a semiconductor device according to a secondembodiment of the present invention;

[0047]FIGS. 3A to 3B are graphical representation each useful in thedeviation amount in the second embodiment of the present invention;

[0048]FIGS. 4A to 4D are cross sectional views showing the steps ofmethod of manufacturing a semiconductor device according to a thirdembodiment of the present invention;

[0049]FIGS. 5A to 5D are cross sectional views showing the steps ofmethod of manufacturing a semiconductor device according to a fourthembodiment of the present invention;

[0050]FIGS. 6A to 6B are graphical representation each useful in thedeviation amount in the fourth embodiment of the present invention; and

[0051]FIGS. 7A to 7D are cross sectional views showing the steps of amethod of manufacturing a semiconductor device according to the priorart.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0052] A first embodiment of the present invention will now be describedin the following. Firstry, a first embodiment of the present inventionwill hereinafter be described with reference to FIGS. 1A to 1E.

[0053] First of all, as shown in FIG. 1A, an element separation film 2on a silicon semiconductor substrate 1 is formed using well knowntechniques, and a gate insulation film 3 is formed to a thickness of30-350 Å using, for example, thermal oxidation of the siliconsemiconductor substrate.

[0054] Next, as shown in FIG. 1B, nitriding is carried out for the gateinsulation film. With this process, a boundary level, trap and unbondedcrystal atoms of the gate insulation film boundary are filled withnitrogen, and the reliability of a gate insulation film with respect tohot electron resistance, etc., is improved. Normally this process iscarried out at an extremely high temperature using RTA (Rapid ThermalAnnealing) such as ramp annealing, for example, processing in an N₂Oatmosphere at 800-1125° C. for 15-120 seconds, processing in an NH₃atmosphere at a temperature of 800-1100° C. for 5-90 seconds, orprocessing in an O₂ atmosphere at a temperature of 800-1125° C. for15-120 seconds.

[0055] Because of the existence of oxygen during the nitriding process,strain does not arise in the silicon semiconductor wafer, and this isparticularly noticeable when processing at a temperature higher than1000° C.

[0056] Next, as shown in FIG. 1C, a gate electrode film 4(a) is formedto a thickness of 1000-4000 Å using, for example, polycrystal silicon.

[0057] Next, as shown in FIG. 1D, using a thermal oxidation furnace,annealing is carried out under an inert gas atmosphere, for exampleunder a nitrogen atmosphere at a temperature of 925-1025° C. for 10-30minutes, or under an argon atmosphere at a temperature of 925-1025° C.for 10-30 minutes.

[0058] Because of this inert gas annealing, strain in the siliconsemiconductor substrate wafer is resolved. Also, since inert gas is usedwith this annealing, there is no inadvertent oxidation of the gateelectrode film 4(a).

[0059] Here, even if inert gas annealing shown in FIG. 1D is carried outafter nitriding processing for the previously mentioned gate insulationfilm 3 and before formation of the gate insulation film 4(a), it goeswithout saying that the effect of resolving strain in the siliconsemiconductor substrate is obtained.

[0060] Moreover, if the quality of the gate insulation film is takeninto consideration, undergoing the annealing process with the gateinsulation film still exposed increases the chances of the gateinsulation film becoming contaminated, which means that from the pointof view of quality it is preferable to perform the inert gas annealingafter formation of the gate electrode film 4(a).

[0061] Continuing on, as shown in FIG. 1E, the gate electrode film 4(a)is patterned and removed by etching to form a transistor gate electrodefilm 4(b), and a MOS transistor comprising a transistor source/drain, aninterlayer insulating film 6, a contact hole 7 and metal wiring 8 isformed by the following well known technique.

[0062] A second embodiment of the present invention, being the firstembodiment applied to an EEPROM cell, will now be described.

[0063] First of all, as shown in FIG. 2A, an element separation film isformed on a silicon semiconductor substrate 9, as required, and a gateinsulation film 10 is formed to a thickness of 200-700 Å by, forexample, thermal oxidation of the silicon semiconductor substrate. Afterthat, a tunnel drain 11 constituting a drain section of a celltransistor of the EEPROM cell is formed by, for example, an ioninjection method, a tunnel window section is formed using a well knowntechnique, and then a tunnel insulation film 12 is formed to a thicknessof 15-120 Å by, for example, thermal oxidation.

[0064] Next, as shown in FIG. 2B, nitriding is carried out for the gateinsulation film at the same time as for the tunnel insulating film. As aresult of this processing, a boundary level, trap, and unbonded crystalatoms of the boundary of the tunnel insulation film and the gateinsulation film are filled with nitrogen, and the resistance tooverwriting, resistance to hot electrons and reliability of each of theinsulation films is improved.

[0065] Normally this process is carried out at an extremely hightemperature using RTA (Rapid Thermal Annealing) such as ramp annealing,for example, processing in an N₂O atmosphere at 800-1125° C. for 15-120seconds, processing in an NH₃ atmosphere at a temperature of 800-1100°C. for 5-90 second, or processing in an O₂ atmosphere at a temperatureof 800-1125° C. for 15-120 seconds.

[0066] Because of the existence of oxygen during the nitriding process,strain does not arise in the silicon semiconductor wafer, and this isparticularly noticeable when processing at a temperature higher than1000° C.

[0067] Next, as shown in FIG. 2C, a gate electrode film 13(a) is formedto a thickness of 1000-4000 Å using, for example, polycrystal silicon.

[0068] Next, as shown in FIG. 2D, using a thermal oxidation furnace,annealing is carried out under an inert gas atmosphere, for exampleunder a nitrogen atmosphere at a temperature of 925-1025° C. for 10-30minutes, or under an argon atmosphere at a temperature of 925-1025° C.for 10-30 minutes.

[0069] Because of this inert gas annealing, strain in the siliconsemiconductor substrate wafer is resolved. Also, since inert gas is usedwith this annealing, there is no inadvertent oxidation of the gateelectrode film 4(a).

[0070] Here, even if inert gas annealing shown in FIG. 2(d) is carriedout after the previously mentioned nitriding processing and beforeformation of the gate insulation film 13(a), it goes without saying thatthe effect of resolving strain in the silicon semiconductor substrate isobtained.

[0071] Also, if the quality of the tunnel insulation film and gateinsulation film are taken into consideration, undergoing the annealingprocess with the gate film surfaces still exposed increases the chancesof each of the gate insulation films becoming contaminated, which meansthat from the point of view of quality it is preferable to perform theinert gas annealing after formation of the gate electrode film 4(a)

[0072] Continuing on, as shown in FIG. 2(e), the gate electrode film ispatterned and removed by etching to form a select gate electrode film13(b) and a floating gate electrode film 13(c) of the EEPROM cell, asource/drain 14 of the EEPROM cell is formed by the following well knowntechnique, and through a gate electrode film interlayer insulation film15 formed on the floating gate electrode film 13(c), a control gateelectrode film 16 is formed using, for example, polycrystal silicon,thus constructing an EEPROM cell comprising an interlayer insulationfilm 17, contact hole 18 and metal wiring 19.

[0073] Here, even in the case where the structure of the EEPROM celluses only single layer polycrystal silicon, it goes without saying thatall of the same effects can be obtained by adopting the presentinvention.

[0074] An example of resolving strain in a silicon semiconductor waferusing the present invention will be shown below.

[0075] A maximum value for an amount of inplane positional variation ofa silicon semiconductor wafer at the time of patterning a gate electrodefilm 13(a) of the second embodiment of the present invention is shown inFIG. 3A, while standard deviation of the inplane positional variation ofthe wafer is shown in FIG. 3B.

[0076] To nitride the gate electrode film, NH₃ and O₂ processing iscarried out. As is clear from the drawing, by carrying out annealingunder a nitrogen atmosphere after the above mentioned nitriding process,the amount of positional variation is improved significantly compared tothe case where the nitriding process is not performed.

[0077] A third embodiment of the present invention will now be describedin the following.

[0078] First of all, as shown in FIG. 4A, an element separation film 21is formed on a silicon semiconductor substrate 20 using a well knowntechnique, and a gate insulation film 22 is formed to a thickness of30-350 Å using, for example, thermal oxidation of the siliconsemiconductor substrate.

[0079] Next, as shown in FIG. 4B, nitriding is carried out for the gateinsulation film. With this process, a boundary level, trap and unbondedcrystal atoms of the gate insulation film boundary are filled withnitrogen, and the reliability of a gate insulation film with respect tohot electron resistance, etc., is improved.

[0080] This process is carried out using RTA (Rapid Thermal Annealing)such as ramp annealing, for example, processing in an N₂O atmosphere ata temperature of 800-1000° C. for 15-120 seconds, processing in an NH₃atmosphere at a temperature of 800 1100° C. for 5-90 seconds, orprocessing in an O₂ atmosphere at a temperature of 800-1000° C. for15-120 seconds.

[0081] Here, since the process temperature under a gas atmospherecontaining nitrogen is less than 1000° C., no strain or slip lines occurin the silicon semicondictor substrate due to the nitriding process.

[0082] Next, as shown in FIG. 4C, a gate electrode film 23(a) is formedto a thickness of 1000-4000 Å using, for example, polycrystal silicon.

[0083] Continuing on, as shown in FIG. 4D, the gate electrode film 23(a)is patterned and removed by etching to form a transistor gate electrodefilm 23(b), and a MOS transistor comprising a transistor source/drain24, an interlayer insulating film 25, a contact hole 26 and metal wiring27 is formed by the following well known technique.

[0084] A fourth embodiment of the present invention, being the thirdembodiment applied to an EEPROM cell, will now be described.

[0085] First of all, as shown in FIG. 5A, an element separation film isformed on a silicon semiconductor substrate 28, as required, and a gateinsulation film 29 is formed to a thickness of 200-700 Å by, forexample, thermal oxidation of the silicon semiconductor substrate. Afterthat, a tunnel drain 30 constituting a drain section of a celltransistor of the EEPROM cell is formed by, for example, an ioninjection method, a tunnel window section is formed using a well knowntechnique, and then a tunnel insulation film 31 is formed to a thicknessof 15-120 Å by, for example, thermal oxidation.

[0086] Next, as shown in FIG. 5B, nitriding is carried out for the gateinsulation film at the same time as for the tunnel insulating film. As aresult of this processing, a boundary level, trap, and unbonded crystalatoms of the boundary of the tunnel insulation film and the gateinsulation film are filled with nitrogen, and the resistance tooverwriting, resistance to hot electrons and reliability of each of theinsulation films is improved.

[0087] This process is carried out using RTA (Rapid Thermal Annealing)such as ramp annealing, for example, processing in an N₂O atmosphere ata temperature of 800-1000° C. for 15-120 seconds, processing in an NH3atmosphere at a temperature of 800 1100° C. for 5-90 seconds, orprocessing in an O₂ atmosphere at a temperature of 800-1000° C. for15-120 seconds.

[0088] Here, since the process temperature under a gas atmospherecontaining nitrogen is less than 1000° C., no strain or slip lines occurin the silicon semicondictor substrate due to the nitriding process.

[0089] Next, as shown in FIG. 5C, a gate electrode film 32(a) is formedto a thickness of 1000-4000 Å using, for example, polycrystal silicon.

[0090] Continuing on, as shown in FIG. 5D, the gate electrode film 32(a)is patterned and removed by etching to form a select gate electrode film32(b) and a floating gate electrode film 32(c) of the EEPROM cell, asource/drain 33 of the EEPROM cell is formed by the following well knowntechnique, and through a gate electrode film interlayer insulation film34 formed on the floating gate electrode film 32(c), a control gateelectrode film 35 is formed using, for example, polycrystal silicon,thus constructing an EEPROM cell comprising an interlayer insulationfilm 36, contact hole 37 and metal wiring 38.

[0091] Here, even in the case where the structure of the EEPROM celluses only single layer polycrystal silicon, it goes without saying thatall of the same effects can be obtained by adopting the presentinvention.

[0092] An example of suppressing strain in a silicon semiconductor waferusing the present invention is shown below.

[0093] A maximum value for an amount of in-plane positional variation ofa silicon semiconductor wafer at the time of patterning a gate electrodefilm 32(a) of the fifth embodiment of the present invention is shown inFIG. 6A, while standard deviation of the in-plane positional variationof the wafer is shown in FIG. 6B.

[0094] In nitriding the gate insulation film, each of NH₃ processing(RTN) and O₂ processing (RTO) are carried out with each of theprocessing times fixed. As is clear from the drawings, after thenitriding process, by carrying out RTO under an O₂ atmosphere at 1000°C. the amount of positional variation is significantly improved, and isat a similar level to when nitriding is not carried out.

[0095] As described above, the present invention maintains positionalaccuracy on a photolithography process at a high level by resolvingstrain of a semiconductor substrate wafer die to annealing in an inertgas atmosphere after a nitriding process, and suppresses the generationof slip lines and suppresses strain in a semiconductor substrate waferby keeping the temperature of processing under a gas atmospherecontaining nitrogen in nitriding processing at less than 1000° C., andso has the following effects.

[0096] 1. With design standards having positioning margins estimated tothe minimum necessary, the level of integration for an IC can beincreased.

[0097] 2. It is possible to make manufacturing yield highly stable.

What is claimed is:
 1. A manufacturing method for a semiconductor devicecomprising a steps of: forming a gate insulation film of MOS transistor,annealing in inert gas, patterning a gate electrode film and removingthe gate electrode film by etching.
 2. The manufacturing method for asemiconductor device as claimed in claim 1 , wherein the inert gas isN₂.
 3. The manufacturing method for a semiconductor device as claimed inclaim 1 , wherein the temperature of annealing with inert gas is atleast 925° C.
 4. The manufacturing method for a semiconductor device asclaimed in claim 2 , further comprising the step of, after formation ofthe insulating gate film, carrying out RTA (Rapid Thermal Annealing) ina gas atmosphere including at least one of nitrogen atoms or oxygenatoms.
 5. The manufacturing method for a semiconductor device as claimedin claim 4 , wherein the inert gas is N₂ or O₂.
 6. The manufacturingmethod for a semiconductor device as claimed in claim 5 , wherein thetemperature of the RTA process is higher than 1000° C.
 7. Themanufacturing method for a semiconductor device as claimed in claim 4 ,wherein, after formation of the insulating gate film over the entiresurface of the semiconductor substrate, annealing is carried out usingan inert gas.
 8. A manufacturing method for a semiconductor device,comprising the step of forming an EEPROM on a semiconductor substrate,between a process of forming a tunnel insulation film and a process ofpatterning a floating gate electrode film and removing the floating gateelectrode film by etching, a step for carrying out annealing using inertgas.
 9. The manufacturing method for a semiconductor device as claimedin claim 8 , wherein the inert gas is N₂.
 10. The manufacturing methodfor a semiconductor device as claimed in claim 8 , wherein thetemperature of annealing with inert gas is at least 925° C.
 11. Themanufacturing method for a semiconductor device as claimed in claim 9 ,including a step of, after formation of the tunnel gate film, carryingout RTA (Rapid Thermal Annealing) in a gas atmosphere including at leastone of nitrogen atoms or oxygen atoms.
 12. The manufacturing method fora semiconductor device as claimed in claim 11 , wherein, after formationof the floating gate electrode film over the entire surface of thesemiconductor substrate, annealing is carried out using an inert gas.13. A manufacturing method for a semiconductor device, comprising thesteps of forming a MOS transistor on a semiconductor substrate, aprocess of forming a gate insulation film and a process of, afterforming the gate insulation film, carrying out heat treatment in a gasatmosphere including oxygen atoms at a temperature of less than 1000° C.14. The manufacturing method for a semiconductor device as claimed inclaim 13 , wherein the inert gas is N₂O.
 15. The manufacturing methodfor a semiconductor device as claimed in claim 13 , wherein the inertgas is O₂.
 16. The manufacturing method for a semiconductor device asclaimed in claim 15 , including, between a step of forming the gateinsulating film and a step of carrying out heat treatment in an O₂atmosphere including a step of carrying out heat treatment in an NH3atmosphere.
 17. The manufacturing method for a semiconductor device asclaimed in claim 13 , wherein the heat treatment at a temperature ofless than 1000° C. is RTA (Rapid Thermal Annealing).
 18. A manufacturingmethod for a semiconductor device, comprising the steps of forming anEEPROM on a semiconductor substrate, a process of forming a gateinsulation film, a process of forming a tunnel insulating film, and aprocess of, after forming the tunnel insulation film, carrying out heattreatment in a gas atmosphere including oxygen atoms at a temperature ofless than 1000° C.
 19. The manufacturing method for a semiconductordevice as claimed in claim 18 , wherein the inert gas is N₂O.
 20. Themanufacturing method for a semiconductor device as claimed in claim 18 ,wherein the inert gas is O₂.
 21. The manufacturing method for asemiconductor device as claimed in claim 20 , including, between a stepof forming the gate insulating film and a step of carrying out heattreatment in an O₂ atmosphere, a step of carrying out heat treatment ina NH₃ atmosphere.
 22. The manufacturing method for a semiconductordevice as claimed in claim 18 , wherein the heat treatment at atemperature of less than 1000° C. is RTA (Rapid Thermal Annealing).